The present invention relates to differential memory cells and, in particular, to an emitter coupled bipolar cell capable of being simultaneously read and written. A register stack constructed from a plurality of the present cells is also disclosed which provides for a master reset, split word write and read enable.
As with all things, a computer's performance is dependent upon the performance of each of its constituent sub-systems. Of such sub-systems, a register stack and/or random access memory is most commonly provided in association with a central processor for making available necessary data to the processor at appropriate times. Accordingly, among other things, it is desirable in advanced computer design to have available a high performance RAM requiring relatively short read and write times.
Alternatively, it is desirable if multiple memory functions can be carried out simultaneously. The obvious advantage is that the designer, relative to other ongoing machine operations, is then able to allow the reading of an addressed memory location, while simultaneously allowing other sub-systems to write either the same memory location or other available memory locations. Timing bottlenecks may thus be reduced, while enhancing system throughput. Heretofore, however, memories capable of truly simultaneous and independent read/write operations were not available to the computer designer.
One attempt at developing such a memory can be found upon directing attention to an article from the IEEE International Solid-State Circuits Conference of 1977 at pages 72-74. There, a 32.times.9 ECL two port complementary memory is disclosed, wherein each memory cell is constructed of four transistors. However, in addition to consuming relatively large amounts of operating power, the cell design is believed deficient in that cell function is restricted in situations where the read address equals the write address or, in other words, where the system simultaneously attempts to read and write the same cell location.
Another example can be found in a 4.times.4 register file such as manufactured by the Amdahl Corporation under part no. AM25LS17O. This device is constructed using integrated injection logic circuitry and which permits a reduction in component numbers. The device circuitry, however, requires the use of Schottky diodes and a large collector dot or hardwired contact between the data output bus which causes the associated memory cells to be relatively slower in comparison to the present memory cells. Also, extraneous collector pullup resistors are required to ensure proper operation.
Yet another attempt at a memory cell capable of independent, simultaneous read and write operations can be found in a 16.times.4 read/write register file manufactured by Fairchild Camera and Instruments Corporation under part no. F100145. Actual device operation however is only pseudo-simultaneous with the array operating in a time-shared fashion. That is, even though a cell location may be simultaneously addressed, operations are only performed sequentially.